Cadence introduced Maestro on October 26, a portfolio of AI models for chip and system design that customers can run in their own data centers. The first models are being offered to selected early-access customers in the fourth quarter of 2026.
The company announcement describes a combination of specialized models, AI agents and engineering software. The agents interpret a design objective, break it into tasks and use Cadence's electronic design automation and system design tools to carry out the work.
Maestro includes Nvidia Nemotron and other models. Customers can further train the portfolio on proprietary designs and workflows. Deployment options include Cadence's cloud, public clouds and a customer-controlled environment on site.
For chipmakers, that gives the announcement a practical focus on where proprietary design data is processed. The customer-controlled option is part of the announced architecture; it does not establish that every customer can obtain the models today.
Cadence reports initial results of up to 30% better quality and up to five times greater token efficiency compared with a general-purpose foundation model. Those are vendor-reported workflow results. Token efficiency measures model usage and should not be read as a promise that a customer's entire chip-design project will cost five times less.
Reuters describes the wider task as arranging billions of transistors to meet cost and performance targets, with software vendors trying to put AI agents in control of more engineering-tool operations.
Cadence's release specifies selected early access during the fourth quarter. It does not announce general availability or public pricing.
